Computing devices are routinely used to store and process a variety of digitally encoded signals. Typically, there are timing requirements related to processing these signals. These timing requirements often involve generating a periodic clock signal that possesses a specific time relationship with respect to a reference signal. As computing systems become more integrated and operate at higher frequencies, the precision required in generating these periodic clock signals becomes more important.
Computing devices typically use conventional delay-locked loops to control the timing of clock signals. FIG. 1 is a block diagram of a conventional delay-locked loop (DLL) 100. Conventional DLL 100 includes delay line 110 and phase detector 120. Delay line 110 has a plurality of delay cells (e.g., delay cells 140A through 140G) and multiplexer 130. A delay cell is an electronic circuit that imparts a delay to signals that pass through the delay cell.
Reference signal 150 provides an input to delay line 110 and phase detector 120. Reference signal 150 is, for example, an internal clock of an integrated circuit. Delay cells 140A through 140G impart a delay time to reference signal 150 as the signal passes through the delay cells. The delay time imparted to reference signal 150 by each delay cell is called a delay period. Typically, the delay period is the same for each delay cell. The output of each delay cell is a signal that is delayed in time and has a significant edge (e.g., rising edge, falling edge, etc.) that is suitable for timing purposes. The term delay edge refers to periodic waveforms having a significant edge (e.g., the outputs of the delay cells).
Delay line 110 provides a delay edge to phase detector 120. Phase detector 120 compares the delay edge to reference signal 150 and provides an output signal that represents the phase difference between the two input signals. The output of phase detector 120 is typically used to generate a voltage-controlled input to the delay cells of delay line 110. The voltage-controlled input determines, in part, which output of the delay cells is selected by multiplexer 130.
Conventional DLL 100 is limited to providing delay edges that are separated by at least one delay period. The ability of conventional DLL 100 to “lock” onto reference signal 150 is limited, therefore, by the width of the delay period. In integrated circuits that are tightly integrated and clocked at high frequencies, conventional DLL 100 may exhibit jitter and slew because the width of the delay period is a relatively coarse increment of change in the amount of delay between delay edges.